sharadsinha

PhD Research

My PhD research revolves around high level synthesis for FPGAs. Most of this research is also applicable to high level synthesis for ASICs. As part of my research, I delve into various sub fields of electronics and computer engineering and science.  I dig into FPGA technologies, programming techniques and paradigms, computational complexity, switching theory, digital design, algorithms for computing various kinds of compute intensive functions and their acceleration, parallel computation, high speed system design, hardware-software partitioning etc.

I also read a lot about current industry standards and practices in these fields to keep my research relevant and focused on future and emerging paradigms. I am an embedded systems guy with more focus on system architecture and hardware design and hence, I am not an expert in software programming languages though I use some of them as and when necessary.

I work with the following tools and languages:

  • Xilinx ISE, Altera Quartus II, Synplify Pro, AutoESL, Synopsys Formality
  • Verilog, VHDL,  C, Perl
  • Modelsim, MATLAB, Altium Designer
  • Valgrind Memory Checker

Google Calendar of ACM Special Interest Group on Design Automation and IEEE CEDA/CAS/CS/DATC Related Conferences:

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