sharadsinha

Publications

Here, you will find my list of publications.There are  different sections based on the different kinds of papers and articles.

Research Publications

J9. Lin Zhe, Sharad Sinha, Liang Hao, Feng Liang and Wei Zhang, “Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multiprocessors”, IEEE Transactions on Multi-Scale Computing Systems (pre-print available in IEEE Xplore)

J8. Liang Hao, Sharad Sinha and Wei Zhang, “Parallelizing hardware tasks on multi-context FPGA with efficient placement and scheduling algorithms”, IEEE Transactions on CAD (pre-print available in IEEE Xplore)

J7. Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang, “HeteroSim: A heterogeneous CPU-FPGA simulator”, IEEE Computer Architecture Letters (IEEE CAL), vol. 16, issue 1, Jan-June 2017, pp. 38-41.

J6. Sharad Sinha and Wei Zhang, “FPGA low power design using memoization based approximate computing”, IEEE Transactions on VLSI (IEEE-TVLSI), vol. 24, issue 8, Aug 2016, pp. 2665-2678.

J5. Sharad Sinha and Thambipillai Srikanthan, “High Level Synthesis: Boosting Designer Productivity and Reducing Time to Market“, IEEE Potentials, vol. 34, issue 4, July-Aug 2015, pp. 31-35.

J4. Sharad Sinha and Thambipillai Srikanthan, “Dataflow graph partitioning for area-efficient  high level synthesis with systems perspective”, ACM Transactions on Design Automation of   Electronic Systems (ACM TODAES), 20, 1, Article 5, November 2014.

J3. Sharad Sinha and Thambipillai Srikanthan, “Architecture and application -aware management of complexity of mapping multiplication to FPGA DSP blocks in high level synthesis“, International Journal of Reconfigurable Computing, vol. 2014, Article ID 564924, 14 pages, 2014.

J2. Sharad Sinha, Udit Dhwan and Thambipillai Srikanthan,  “Extended compatibility path based hardware binding: an adaptive algorithm for high level synthesis of area-time efficient designs“, Journal of Circuits, Systems and Computers, vol. 23, no. 9, Article 1450131, October 2014.

J1. Sharad Sinha and Thambipillai Srikanthan, “IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance,” International Journal of Reconfigurable Computing, vol. 2014, Article ID 418750, 17 pages, 2014. doi:10.1155/2014/418750.

 

Conferences

C14. Jieru Zhao, Feng Liang, Sharad Sinha and Wei Zhang, “COMBA: a comprehensive model based analysis framework for high level synthesis of real applications“, 36th IEEE ACM International Conference on Computer Aided Design (ICCAD 2017) (Accepted) (2017 IEEE/ACM WILLIAM J. MCCALLA ICCAD BEST PAPER AWARD (Front End))

C13. Lin Zhe, Sharad Sinha and Wei Zhang, “Decision tree based hardware power monitoring for run time dynamic power management in FPGA“, 27th International Conference on Field Programmable Logic and Applications (FPL 2017) (Accepted)

C12. Tingyuan Liang, Feng Liang, Sharad Sinha and Wei Zhang, “gem5-HDL: system simulation and exploration for programmable heterogeneous systems“,27th International Conference on Field Programmable Logic and Applications (FPL 2017) (Accepted)

C11. Liang Feng, Liang Hao, Sharad Sinha and Wei Zhang, “HeteroSim: A heterogeneous CPU-FPGA simulator“, 26th International Conference on Field Programmable Logic and Applications (FPL 2016(Accepted) (Demo Paper)

C10. Mohammad Tahghighi, Wei Zhang and Sharad Sinha, “Area efficient hardware architecture for implicitly defined complex events processing“, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2016) (Accepted)

C9. Liang Hao, Sharad Sinha, Rakesh Warrier and Wei Zhang, “Static hardware task placement on multi-context FPGA using hybrid genetic algorithm“, 25th International Conference on Field Programmable Logic and Applications (FPL 2015), 2-4 Sept. 2015, London, pp. 1-8.

C8. Sharad Sinha and Wei Zhang, “SynDFG: A synthetic dataflow graph generator for high level synthesis“, 6th Asia Symposium on Quality Electronic Design (ASQED 2015) , Kuala Lumpur, August 2015, pp. 50-55.

C7. Sharad Sinha and Thambipillai Srikanthan, “Constraint-aware synthesis of embedded applications on reconfigurable platforms“, PhD Forum, International Conference on Field Programmable Technology (FPT 2012), Seoul, South Korea, Dec 10-12, 2012.

C6. Sharad Sinha and Thambipillai Srikanthan, “Dataflow graph partitioning for high level synthesis“, 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, Oslo, Norway, August 29-31,2012, pp 503-506.

C5. Sharad Sinha,Udit Dhawan, Siew-Kei Lam and Thambipillai Srikanthan, “A novel algorithm to reduce critical path delay during high level synthesis“, IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2011),  Chennai, India, July 4-6, 2011, pp 278-283.

C4. Sharad Sinha, Thambipillai Srikanthan, “A framework for high level synthesis of transcendental functions“,  International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2011), Hsinchu, Taiwan, April 25-28, 2011, pp 1-4.

C3. Sharad Sinha, Thambipillai Srikanthan, “Hardware complexity metrics for high level synthesis of software functions“, International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2011, Hsinchu, Taiwan, April 25-28, 2011, pp 1-4.

C2. Udit Dhawan, Sharad Sinha, Siew-Kei Lam and Thambipillai Srikanthan, “Extended compatibility path based hardware binding algorithm for area-time efficient designs“, 2nd Asia Symposium on Quality Electronic Design (ASQED 2010), Penang, Malaysia, August 3-5,2010, pp 151-156.

C1. P.Mythili, Sharad Sinha, Chitra P.Chandran, “A Novel Approach to Low Power Analog Circuit Synthesis using Genetic Algorithms”, 13th NASA Symposium on Low Power VLSI, June 5-6, Idaho, USA, 2007. (B.Tech Project Publication)

Exploratory Ideas (Science, Technology and Society : Online; Peer Reviewed)

2. Sharad Sinha, “Data analytics for public services: beyond the hype”, ACM Ubiquity Blogs, Jan. 11, 2017. (read it here)

1. Sharad Sinha, “Can chatbots replace customer service reps”, ACM Ubiquity BlogsNov. 15, 2016. (read it here)

Industrial Design Magazines

8. Sharad Sinha, “NBTI and FPGA Design“, Circuit Cellar (issue 276), July 2013, pp. 30-33.

7. Sharad Sinha, “Xilinx high level synthesis tool speeds FPGA design“, Xcell Journal, issue 83, 2nd Quarter 2013, pp. 32-39.

6. Sharad Sinha, “Understanding the major clock resources in Xilinx FPGAs“, Xcell Journal, issue 81, 4th Quarter 2012, pp. 37-41.

5. Sharad Sinha, “Tips and tricks for better floating point calculations in embedded systems“, Xcell Journal, issue 78, 1st Quarter 2012, pp. 48-51.

4. Sharad Sinha, “Using the clock period constraint to your advantage“, Xcell Journal, issue 77, 4th Quarter 2011, pp. 46-49.

(Also available online at EE Times here)

3. Sharad Sinha, “Area efficient Design of the SAD function on FPGAs“, Xcell Journal, issue 75, 2nd Quarter 2011, pp. 38-43.

2. Sharad Sinha, “Designing with FPGAs: A Step by Step Guide to Embedded Development”, Circuit Cellar (Issue 222),  January 2009, pp. 38-43.

1. Sharad Sinha, “Verification and Simulation of FPGA Designs“, Circuit Cellar (Issue 230),  September 2009, pp. 85.

Publications on the subject of Education

8. Sharad Sinha, “My first lecture and other lessons in teaching”, IEEE Potentials, (May-June 2017; to be published).

7. Sharad Sinha, “Industry consortium: a source for education and research”, IEEE Potentials, vol. 35, issue 3, May-June 2016, pp. 23-26.

6. Sharad Sinha, “What and what not to expect from your PhD advisor“, IEEE Potentials, vol. 34, issue 3, May-June 2015, pp. 22-24.

5. Sharad Sinha and Mahdi Nikdast, “Finding happiness and satisfaction during your PhD program“, IEEE Potentials, vol. 34, issue 3, May-June 2015, pp. 36-38.

4. Sharad Sinha, “Using your PhD Experience as a catalyst for change“, IEEE Potentials, vol. 33, issue 3, June 2014, pp. 23-24.

3. Sharad Sinha, “The benefits of volunteering“, IEEE Potentials , vol. 33, issue 3, June 2014, pp. 30-31.

2. Sharad Sinha, “Understanding industrial espionage for greater technological and economic security“, IEEE Potentials, vol.31, issue 3, May-Jun 2012, pp. 37-41. (has some technical details too)

1. Sharad Sinha, “A greater role for IEEE student branches”, IEEE Potentials, vol.25, no. 6, Nov-Dec 2006, pp. 4.

Editorials
2. Sharad Sinha, “Advanced/Smart Manufacturing: From nanoscale to megascale”, IEEE Potentials, vol. 25, issue 4, July-Aug. 2016, pp. 7-8.
(As part of the themed issue on “Advanced/Smart Manufacturing” under my initiative)
1. Sharad Sinha, “Engineer and artist: a promising collaboration“, IEEE Potentials, vol.34, issue. 6, Nov-Dec 2015, pp. 6-7.
(As part of the themed issue on “Art and Engineering” under my initiative)
Last Updated: December 26, 2016
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